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40313hkim 20120403-s00001 no.a2175-1/23 semiconductor components industries, llc, 2013 april, 2013 http://onsemi.com lc87f2608a overview the lc87f2608a is an 8-bit microcontroller that, centered around a cpu running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 8k-byte fl ash rom, 512-byte ram, an on-chip debugger, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a synchronous sio interface, a high-speed 12-bit pwm, two high-speed pulse width/period counters, a 3-channel ad converter with 12-/8-bit resolution selector, an analog co mparator, a watchdog timer, an internal reset circuit, a system clock frequency divider, and a 16-source 10-vector interrupt feature. features ? flash rom ? 8192 8 bits (lc87f2608a) ? capable of on-board-programming with wide range of voltage source (3.0 to 5.5v). ? block-erasable in 128-byte units ? ram ? 512 9 bits (lc87f2608a) ? package form ? mfp10sk: lead-/halogen-free type ? mfp14s (for debugging only): lead-free type ? mfp10s: lead-/halogen-free type (discontinued) package dimensions package dimensions unit : mm (typ) unit : mm (typ) 3111a (for debugging only) 3086b (discontinued) orderin g numbe r : ENA2175 cmos ic 8k-byte from and 512-byte ram integrated 8-bit 1-chip microcontroller mfp10s(225mil) 1 10 5 6 (0.5) 1.7max 1.0 0.35 5.0 0.15 6.4 (1.5) 0.1 4.4 0.63 mfp14s(225mil) 1 14 7 8 8.0 0.15 (1.0) 1.0 0.35 1.7max (1.5) 0.1 4.4 0.63 6.4 * this product is licensed from silicon storage technology, inc. (usa). package dimensions unit : mm (typ) 3420 mfp10sk(225mil) 1 10 2 0.8 max 1.55 1.0 0.35 5.0 0.15 6.2 (1.5) 0.05 4.4 0.5
lc87f2608a no.a2175-2/23 ? minimum bus cycle time (note1) ? 100ns (10mhz) v dd =2.7 to 5.5v (note2) ? minimum instruction cycle time ? 300ns (10mhz) v dd =2.7 to 5.5v (note2) note1: the bus cycle time here refers to the rom read speed. note2: use this product in a voltage range of 3.0 to 5.5v because the minimum release voltage (porrl) of the power-on reset (por) circuit is 2.87v0.12v. ? ports ? i/o ports ports whose i/o direction can be designated in 1 bit units: 7 (p10 to p12, p30 to p33) ? reset pins: 1 ( res ) ? power pins: 2 (v ss 1, v dd 1) ? timers ? timer 0: 16-bit timer/counter with a capture register mode 0: 8-bit timer with an 8-bit programmable pres caler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter mode 0: 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler mode 2: 16-bit timer/counter with an 8-bit prescaler ? serial interface ? sio7: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) ? high-speed 12-bit pwm ? system clock/high-speed rc oscillation clock (20mhz or 40mhz) operation selectable ? duty/period programmable ? continuous pwm output/specific count pwm output (automatic stop) selectable ? high-speed pulse width/period counter ? hct1: high-speed pulse width/period counter 1 1) system clock/high-speed rc oscillation clock (20mhz or 40mhz) operation selectable 2) h-level width/l-level width/period measurement modes selectable 3) input triggering noise filter ? hct2: high-speed pulse width/period counter 2 1) system clock/high-speed rc oscillation clock (20mhz or 40mhz) operation selectable 2) can measure both l-level width and period simultaneously. 3) input triggering noise filter 4) input trigger selectable (from 3 signals, i.e., p11/hct2in, p31/hct2in, and analog comparator output)
lc87f2608a no.a2175-3/23 ? ad converter: 12 bits 3 channels ? 12-/8-bit ad converter resolution selectable ? analog comparator ? sends output to the p32/cmpo port (polarity selectable). ? edge detection function (shared with intc and also allows the selection of the noise filter function) ? watchdog timer ? can generate the internal reset signal on a timer ove rflow monitored by the wdt-dedicated low-speed rc oscillation clock (30khz). ? allows selection of continue, stop, or hold mode operation of the counter on entry into the halt/ hold mode. ? interrupt source flags ? 16 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt control. any interrupt requests of the level equal to or lo wer than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l inta 2 0000bh x or l intb 3 00013h h or l intc/t0l/inte 4 0001bh h or l intd/intf 5 00023h h or l t0h/sio7 6 0002bh h or l t1l/t1h 7 00033h h or l hct1 8 0003bh h or l hct2 9 00043h h or l adc/hpwm automatic stop/hpwm cycle 10 0004bh h or l none ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 256 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? medium speed rc oscillation circuit (internal): for system clock (1mhz) ? low speed rc oscillation circuit (internal): for watchdog timer (30khz) ? high speed rc oscillation circuit (internal): for system clock (20mhz or 40mhz) 1) 2 source oscillation frequencies (20mhz or 40mhz) se lectable for the high-speed rc oscillation circuit by optional configuration. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (when high speed rc oscillation is selected for system clock.).
lc87f2608a no.a2175-4/23 ? internal reset circuit ? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 3 levels (2.87v, 3.86v, and 4.35v) by optional configuration. ? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use or disuse of the lvd function and the low voltage threshold level (3 levels: 2.81v, 3.79v, and 4.28v) can be selected by optional configuration. ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are the following three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) generating a reset signal via the watchdog timer or brown-out detector (3) having an interrupt generated ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the medium- and high-speed rc oscillation circuits automatically stop operation. 2) there are the following four ways of resetting the hold mode. (1) setting the reset pin to the low level (2) generating a reset signal via the watchdog timer or brown-out detector (3) setting at least one of the inta, intb, intc, in td, inte, and intf pins to the specified level (inta and intb hold mode reset is available only when level detection is set.) (4) applying input signals to the in+ and in- pins so that th e analog comparator output is set to the specified level (when the analog comparator output is assigned to the intc input) ? on-chip debugger function ? supports software debugging with the ic mounted on the target board (selectable from 3 series). 1) lc87d2708a : all terminal function of lc87f2608a can be used. 2) lc87f2708a : all terminal function of lc87f2608a can be used. the debug feature is limited. 3) lc87f2608a : the debugger terminal function when an on-chip debugger is used cannot be used. the debug feature is limited. ? two channels of on-chip debugger pins are available (lc87f2608a). ? data security function (note3) ? protects the program data stored in flash memory from unauthorized read or copy. note3: this data security function does not necessarily provide absolute data security.
lc87f2608a no.a2175-5/23 ? development tools ? on-chip debugger: 1) tcb87-type b + lc87d2708a or lc87f2708a 2) tcb87-type b + lc87f2608a 3) tcb87-type c (3 wire version) + lc87d2708a or lc87f2708a 4) tcb87-type c (3 wire version) + lc87f2608a ? programming board package programming board mfp10s w87f27m-dbg mfp10sk mfp14s ? flash rom programming board maker model version device flash support group, inc. (fsg) + our company (note 4) in-circuit programmer af9101/af9103 (main body) (fsg models) rev.01.01 or later lc87f2608a sib87 (inter face driver) (our company model) our company single/gang programmer skk-dbg type b (sanyo fws) application version 1.04 or later chip data version 2.10 or later lc87f2608a in-circuit/ gang programmer for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note4: on-board-programmer from fsg (af9101/af9103) an d serial interface driver from our company (sib87) together can give a pc-less, standalone on-board-programming capabilities.
lc87f2608a no.a2175-6/23 pin assignment mfp10s ?lead-/halogen-free type? mfp10sk ?lead-/halogen-free type? mfp10s mfp10sk name 1 p31/intb/hct2in/dbgp01 2 p30/inta/hct1in/dbgpx0 3 res 4 p10/so7/inte/an0/dbgp02 5 v ss 1 6 p12/sck7/intf/in-/an2 7 p11/si7/sb7/inte /in+/hct2in/an1 8 p33/intd/hpwm/dbgp12 9 p32/intc/cmpo/dbgp11 10 v dd 1 p31/intb/hct2in/dbgp01 p30/inta/hct1in/dbgpx0 res p10/so7/inte/an0/dbgp02 v ss 1 v dd 1 p32/intc/cmpo/dbgp11 p33/intd/hpwm/dbgp12 p11/si7/sb7/inte/in+/hct2in/an1 p12/sck7/intf/in-/an2 1 2 3 4 5 10 9 8 7 6
lc87f2608a no.a2175-7/23 mfp14s (for debugging only) ?lead-free type? mfp14s name 1 p31/intb/hct2in/dbgp01 2 p30/inta/hct1in/dbgpx0 3 res 4 p10/so7/inte/an0/dbgp02 5 v ss 1 6 nc 7 dbgp22 8 dbgp21 9 dbgp20 10 p12/sck7/intf/in-/an2 11 p11/si7/sb7/inte /in+/hct2in/an1 12 p33/intd/hpwm/dbgp12 13 p32/intc/cmpo/dbgp11 14 v dd 1 p31/intb/hct2in/dbgp01 p30/inta/hct1in/dbgpx0 res p10/so7/inte/an0/dbgp02 v ss 1 nc dbgp22 v dd 1 p32/intc/cmpo/dbgp11 p33/intd/hpwm/dbgp12 p11/si7/sb7/inte/in+/hct2in/an1 p12/sck7/intf/in-/an2 dbgp20 dbgp21 1 2 3 4 5 6 7 14 13 12 11 10 9 8
lc87f2608a no.a2175-8/23 system block diagram interrupt control standby control ir pla flash rom pc bus interface port 1 (inte-intf) port 3 (inta-intd) sio7 timer 0 timer 1 high-speed pwm high-speed pulse width/period counter1 adc high-speed pulse width/period counter2 acc b register c register psw rar ram stack pointer alu on-chip debugger medium- speed rc freq. divider clock generator reset circuit (lvd/por) wdt (low-speed rc) reset control res data bus data bus analog comparator high-speed rc
lc87f2608a no.a2175-9/23 pin description pin name i/o description option v ss 1 - - power supply pin no v dd 1 - + power supply pin no port1 p10 to p12 i/o ? 3-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? multiplexed pins p10: sio7 data output/ inte input/hold release input/timer 1 event input/ timer 0l capture input/timer 0h capture input p11: sio7 data input/bus i/o/ high-speed pulse width/period counter 2 inpu/t inte input/hold release input/timer 1 event input/ timer 0l capture input/timer 0h capture input p12: sio7 clock i/o/ intf input/hold release input/timer 1 event input/ timer 0l capture input/timer 0h capture input ad converter input ports: an0 to an2 (p10 to p12) analog comparator input por ts: in+, in- (p11, p12) on-chip debugger pin 1: dbgp02 (p10) ? interrupt acknowledge type rising falling rising & falling h level l level inte intf enable enable enable enable enable enable disable disable disable disable yes port3 p30 to p33 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? multiplexed pins p30: inta input/hold release input/timer 0l capture input/ high-speed pulse width/period counter 1 input p31: intb input/hold release input/timer 0h capture input/ high-speed pulse width/period counter 2 input p32: intc input/hold release input/timer 0 event input/ timer 0l capture input/analog comparator output p33: intd input/hold release input/timer 0 event input/ timer 0h capture input/high-speed pwm output on-chip debugger pin 1: dbgpx0 to dbgp01 (p30 to p31) on-chip debugger pin 2: dbgpx0 to dbgp12 (p30, p32 to p33) ? interrupt acknowledge type rising falling rising & falling h level l level inta intb intc intd enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable yes res i/o external reset input/internal reset output no
lc87f2608a no.a2175-10/23 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p10 to p12 1 bit 1 cmos programmable 2 n-channel open drain programmable p30 to p33 1 bit 1 cmos programmable 2 n-channel open drain programmable on-chip debugger pin processing for the processing of the on-chip debugger pins, refer to the separately available documents entitled "rd87 on-chip debugger installation" and "lc872000 series on-chip debugger pin processing." recommended unused pin connections pin name recommended unused pin connections board software p10 to p12 open set output low p30 to p33 open set output low user options option name option type flash version option switched in unit of description port output type p10 to p12 enable 1bit cmos n-channel open drain p30 to p33 enable 1bit cmos n-channel open drain program start address - enable - 00000h 01e00h brown-out detector reset function brown-out detector function enable - enable: used disable: not used brown-out trip level enable - 3 levels power-on-reset function power-on-reset level enable - 3 levels high-speed rc oscillator circuit oscillation frequency enable - 20 mhz 40 mhz package type - enable - mfp10s: lc87f2608a mfp14s: debugged by using lc87d2708a or lc87f2708a
lc87f2608a no.a2175-11/23 absolute maximum ratings at ta=25 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1 -0.3 to +6.5 v input voltage v i res -0.3 to v dd +0.3 input/output voltage v io ? port 1 ? port 3 -0.3 to v dd +0.3 high level output current peak output current i oph (1) port 1 ? cmos output selected ? per applicable pin -7.5 ma i oph (2) port 3 ? cmos output selected ? per applicable pin -10 mean output current (note 1-1) i omh (1) port 1 ? cmos output selected ? per applicable pin -5 i omh (2) port 3 ? cmos output selected ? per applicable pin -7.5 total output current i oah (1) ? port 10 ? ports 30, 31 total of currents at all applicable pins -20 i oah (2) ? ports 11, 12 ? ports 32, 33 total of currents at all applicable pins -20 i oah (3) ? port 1 ? port 3 total of currents at all applicable pins -35 low level output current peak output current i opl (1) port 1 per applicable pin 15 i opl (2) port 3 per applicable pin 10 mean output current (note 1-1) i oml (1) port 1 per applicable pin 10 i oml (2) port 3 per applicable pin 7.5 total output current i oal (1) ? port 10 ? ports 30, 31 total of currents at all applicable pins 25 i oal (2) ? ports 11, 12 ? ports 32, 33 total of currents at all applicable pins 35 ioal (3) ? port 1 ? port 3 total of currents at all applicable pins 55 power dissipation pd max(1) mfp10s ? ta=-40 to +85 c ? independent package 100 mw pd max(2) ? ta=-40 to +85 c ? mounted on thermal test board (note 1-2) 237 pd max(3) mfp10sk ? ta=-40 to +85 c ? independent package 100 pd max(4) ? ta=-40 to +85 c ? mounted on thermal test board (note 1-2) 237 operating ambient temperature topr -40 to +85 c storage ambient temperature tstg -55 to +125 note 1-1: mean output current refers to the average of output currents measured for a period of 100ms. note 1-2: thermal test board used conforms to semi (size: 76.1 114.3 1.6tmm, glass epoxy board). stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lc87f2608a no.a2175-12/23 allowable operating conditions at ta= -40 to +85 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) v dd v dd 1 0.272 s tcyc 100 s 2.7 5.5 v memory sustaining supply voltage v hd v dd 1 ram and register contents sustained in hold mode 2.0 5.5 high level input voltage v ih (1) ? port 1 ? port 3 output disabled 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) res 2.7 to 5.5 0.75v dd v dd low level input voltage v il (1) ? port 1 ? port 3 output disabled 4.0 to 5.5 v ss 0.1v dd +0.4 2.7 to 4.0 v ss 0.2v dd v il (2) res 2.7 to 5.5 v ss 0. 25v dd instruction cycle time (note 2-2) tcyc 2.7 to 5.5 0.272 100 s oscillation frequency range fmhrc(1) ? high-speed rc oscillation ? 40mhz selected as option ? ta=-20 to +85 c 4.5 to 5.5 38 40 42 mh z fmhrc(2) ? high-speed rc oscillation ? 40mhz selected as option ? ta=-40 to +85 c 4.5 to 5.5 37.6 40 42.4 fmhrc(3) 3.5 to 5.5 36.8 40 43.2 fmhrc(4) 2.7 to 5.5 32 40 43.2 fmhrc(5) ? high-speed rc oscillation ? 20mhz selected as option ? ta=-20 to +85 c 3.0 to 5.5 19 20 21 fmhrc(6) ? high-speed rc oscillation ? 20mhz selected as option ? ta=-40 to +85 c 2.7 to 5.5 18.7 20 21.3 fmrc medium-speed rc oscillati on 2.7 to 5.5 0.5 1.0 2.0 fmslrc low-speed rc oscillation 2.7 to 5.5 15 30 60 khz oscillation stabilization time tmshrc ? when high-speed rc oscillation state is switched from stopped to enabled. ? see fig. 2. 2.7 to 5.5 100 s note 2-1: use this product in a voltage range of 3.0 to 5.5v because the minimum release voltage (porrl) of the power-on reset (por) circuit is 2.87v0.12v. note 2-2: relationship between tcyc and oscillation frequency is as follows: ? when system clock source is set to medium-speed rc oscillation 3/fmrc at a division ratio of 1/1, 6/fmrc at a division ratio of 1/2, 12/fmrc a division ratio of 1/4, and so forth ? when system clock source is set to high-speed rc os cillation (40mhz selected by optional configuration) 12/fmhrc at a division ratio of 1/1, 24/fmhrc at a division ratio of 1/2, 48/fmhrc a division ratio of 1/4, and so forth ? when system clock source is set to high-speed rc os cillation (20mhz selected by optional configuration) 6/fmhrc at a division ratio of 1/1, 12/fmhrc at a division ratio of 1/2, 24/fmhrc a division ratio of 1/4, and so forth
lc87f2608a no.a2175-13/23 electrical characteristics at ta= -40 to +85 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ? port 1 ? port 3 ? output disabled ? pull-up resistor off ? v in =v dd (including output tr. off leakage current) 2.7 to 5.5 1 a i ih (2) res v in =v dd 2.7 to 5.5 1 low level input current i il ? port 1 ? port 3 ? output disabled ? pull-up resistor off ? v in =v ss (including output tr. off leakage current) 2.7 to 5.5 -1 high level output voltage v oh (1) cmos output type port 1 i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.35ma 2.7 to 5.5 v dd -0.4 v oh (3) cmos output type port 3 i oh =-5ma 4.5 to 5.5 v dd -1.5 v oh (4) i oh =-0.7ma 2.7 to 5.5 v dd -0.4 low level output voltage v ol (1) port 1 i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.4ma 2.7 to 5.5 0.4 v ol (3) port 3 i ol =5ma 4.5 to 5.5 1.5 v ol (4) i ol =0.7ma 2.7 to 5.5 0.4 pull-up resistance rpu(1) ? port 1 ? port 3 v oh =0.9v dd 4.5 to 5.5 15 35 80 k ? rpu(2) 2.7 to 4.5 18 50 150 rpu(3) res 2.7 to 5.5 216 360 504 hysteresis voltage vhys ? port 1 ? port 3 ? res 2.7 to 5.5 0.1v dd v pin capacitance cp all pins ? vin=vss for pins other than that under test ? f=1 mhz ? ta=25 c 2.7 to 5.5 10 pf
lc87f2608a no.a2175-14/23 serial i/o characteristics at ta= -40 to +85 c, v ss 1=0v sio7 serial i/o characteristics (note 4-1-1) parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck7(p12) ? see fig. 4. (note 4-1-2) 2.7 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 output clock frequency tsck(2) sck7(p12) ? cmos output selected ? see fig. 4. 2.7 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 serial input data setup time tsdi(1) sb7(p11), si7(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 4. 2.7 to 5.5 0.03 s data hold time thdi(1) 0.03 serial output input clock output delay time tddo(1) so7(p10), sb7(p11) ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 4. 2.7 to 5.5 1tcyc +0.05 output clock tddo(2) (1/3)tcyc +0.05 note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in transm ission/reception mode, the time from si7run being set when serial clock is "h" to the first falling edge of the serial clock must be longer than 1tcyc.
lc87f2608a no.a2175-15/23 pulse input conditions at ta= -40 to +85 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) inta(p30), intb(p31), intd(p33), inte(p10, p11), intf(p12) ? interrupt source flag can be set. ? event inputs for timers 0 and 1 are enabled. 2.7 to 5.5 1 tcyc tpih(2) tpil(2) intc(p32) when noise filter time constant is "none" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 1 tpih(3) tpil(3) intc(p32) when noise filter time constant is "1/16" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) intc(p32) when noise filter time constant is "1/32" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 128 tpih(5) tpil(5) intc(p32) when noise filter time constant is "1/64" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tpih(6) tpil(6) hct1in(p30) pulses can be recognized as signals by the high-speed pulse width/period counter 1. 2.7 to 5.5 3 h1ck (note 5-1) tpih(7) tpil(7) hct2in(p11, p31) pulses can be recognized as signals by the high-speed pulse width/period counter 2. 2.7 to 5.5 6 h2ck (note 5-2) tpil(8) res resetting is enabled. 2.7 to 5.5 200 s note 5-1: h1ck denotes the period of the base clock (1 to 8 high-speed rc oscillation clock or system clock) for the high-speed pulse width/period counter 1. note 5-2: h2ck denotes the period of the base clock (2 to 16 high-speed rc oscillation clock or system clock) for the high-speed pulse width/period counter 2. comparator characteristics at ta= -40 to +85 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit common mode input voltage range vcmin in+(p11), in-(p12) 2.7 to 5.5 v ss v dd -1.5 v offset voltage voff within common mode input voltage range 2.7 to 5.5 10 30 mv response time trt ? within common mode input voltage range ? input amplitude=100mv ? overdrive=50mv 2.7 to 5.5 200 600 ns operation stabilization time (note 6-1) tcmw 2.7 to 5.5 1.0 s note 6-1: the interval after cmpon is set till the operation gets stabilized.
lc87f2608a no.a2175-16/23 ad converter characteristics at v ss 1=0v <12-bit ad conversion mode at ta=-40 to +85 c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p10) to an2(p12) 3.0 to 5.5 12 bit absolute accuracy et (note 7-1) 3.0 to 5.5 16 lsb conversion time tcad ? see "conversion time calculation method." (note 7-2) 4.0 to 5.5 38 104.3 s 3.0 to 5.5 75.8 104.3 analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain= v dd 3.0 to 5.5 1 a iainl vain= v ss 3.0 to 5.5 -1 <8-bit ad converter mode at ta=-40 to +85 c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p10) to an2(p12) 3.0 to 5.5 8 bit absolute accuracy et (note 7-1) 3.0 to 5.5 1.5 lsb conversion time tcad ? see "conversion time calculation method." (note 7-2) 4.0 to 5.5 23.4 64.3 s 3.0 to 5.5 46.7 64.3 analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain= v dd 3.0 to 5.5 1 a iainl vain= v ss 3.0 to 5.5 -1 12-bit ad conversion mode: tcad (conversi on time) = ((52/(division ratio)) + 2) (1/3) tcyc 8-bit ad conversion mode: tcad (conversion time) = ((32/(division ratio)) + 2) (1/3) tcyc high-speed rc oscillation (fmhrc) supply voltage range (v dd ) system clock division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) conversion time (tcad) 12-bit ad 8-bit ad 40mhz/20mhz 4.0v to 5.5v 1/1 300ns 1/8 41.8 s 25.8 s 3.0v to 5.5v 1/1 300ns 1/16 83.4 s 51.4 s note 7-1: the quantization error (1/2lsb ) is excluded from the absolute accuracy . the absolute accuracy is measured when no change occurs in the i/o state of the pins that are adjacent to the analog input channel during ad conversion processing. note 7-2: the conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital conversion value against the analog input value is loaded in the result register. *the conversion time is twice the normal value when one of the following conditions occurs: ? the first ad conversion executed in the 12-b it ad conversion mode after a system reset. ? the first ad conversion executed after the ad conversion mode is switched from 8-bit to 12-bit ad conversion mode.
lc87f2608a no.a2175-17/23 power-on reset (por) characteristics at ta= -40 to +85 c, v ss 1=0v parameter symbol pin/remarks conditions specification option selecting voltage min typ max unit por release voltage porrl ? option selected ? see fig. 6. (note 8-1) 2.87v 2.75 2.87 2.99 v 3.86v 3.73 3.86 3.99 4.35v 4.21 4.35 4.49 unknown voltage area pouks ? see fig. 6. (note 8-2) 0.7 0.95 power startup time poris power startup time from v dd =0v to 2.8v 100 ms note 8-1: the por release voltage can be selected from three levels when the low-voltage detection feature is deselected. note 8-2: there is an unpredictable period before the power-on reset transistor starts to turn on. low-voltage detection (lvd) characteristics at ta=-40 to +85 c , v ss 1=0v parameter symbol pin/remarks conditions specification option selecting voltage min typ max unit lvd reset voltage (note 9-2) lvdet ? option selected ? see fig. 7. (note 9-1) (note 9-3) 2.81v 2.71 2.81 2.91 v 3.79v 3.69 3.79 3.89 4.28v 4.18 4.28 4.38 lvd voltage hysteresis lvhys 2.81v 60 mv 3.79v 65 4.28v 65 unknown voltage area lvuks ? see fig. 7. (note 9-4) 0.7 0.95 v minimum low voltage detection width (response sensitivity) tlvdw ? lvdet-0.5v ? see fig. 8. 0.2 ms note 9-1: the lvd reset voltage can be selected from three levels when the low- voltage detection feature is selected. note 9-2: the hysteresis voltage is not included in the lvd reset voltage value. note 9-3: there are cases when the lvd reset voltage value is exceeded when a greater change in the output level or large current is applied to the port. note 9-4: there is an unpredictable period before the lo w-voltage detection resetting transistor starts to run.
lc87f2608a no.a2175-18/23 consumption current characteristics at ta=-40 to +85 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 10-1) iddop(1) v dd 1 ? fmhrc=40mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/4 of 40mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 7.8 14 ma iddop(2) 2.7 to 3.6 4.9 9.4 iddop(3) ? fmhrc=20mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/2 of 20mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 7.1 12.8 iddop(4) 2.7 to 3.6 4.5 8.6 iddop(5) ? high-speed rc oscillation stopped ? system clock set to medium-speed rc oscillation mode ? system clock frequency division ratio set to 1/2 4.5 to 5.5 0.60 1.9 iddop(6) 2.7 to 3.6 0.38 1.3 halt mode consumption current (note 10-1) iddhalt(1) halt mode ? fmhrc=40mhz oscillation mode ? system clock set to high-speed rc, 10mhz(1/4 of 40mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 3.2 5.0 iddhalt(2) 2.7 to 3.6 2.0 3.1 iddhalt(3) halt mode ? fmhrc=20mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/2 of 20mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 2.5 3.9 iddhalt(4) 2.7 to 3.6 1.6 2.5 iddhalt(5) halt mode ? high-speed rc oscillation stopped ? system clock set to medium-speed rc oscillation mode ? system clock frequency division ratio set to 1/2 4.5 to 5.5 0.32 1.0 iddhalt(6) 2.7 to 3.6 0.16 0.55 hold mode consumption current (note 10-1) iddhold(1) hold mode ? ta=-10 to +50 c 4.5 to 5.5 0.04 3.0 a iddhold(2) 2.7 to 3.6 0.02 1.8 iddhold(3) hold mode ? ta=-40 to +85 c 4.5 to 5.5 0.04 34 iddhold(4) 2.7 to 3.6 0.02 22 iddhold(5) hold mode ? lvd option selected ? ta=-10 to +50 c 4.5 to 5.5 3.1 6.8 iddhold(6) 2.7 to 3.6 2.4 4.2 iddhold(7) hold mode ? lvd option selected ? ta=-40 to +85 c 4.5 to 5.5 3.1 39 iddhold(8) 2.7 to 3.6 2.4 25 iddhold(9) hold mode ? watchdog timer active ? ta=-10 to +50 c 4.5 to 5.5 3.4 10 iddhold(10) 2.7 to 3.6 1.7 6.0 iddhold(11) hold mode ? watchdog timer active ? ta=-40 to +85 c 4.5 to 5.5 3.4 42 iddhold(12) 2.7 to 3.6 1.7 27 iddhold(13) hold mode ? comparator active (in+= v dd , in-= v ss ) 4.5 to 5.5 110 160 iddhold(14) 2.7 to 3.6 65 100 note 10-1: the consumption current value includes none of the currents that flow into the output tr and internal pull-up resistors.
lc87f2608a no.a2175-19/23 f-rom programming characteristics at ta=+10 to +55 c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw v dd 1 ? microcontroller consumption current is excluded. 3.0 to 5.5 5 10 ma programming time tfw(1) ? erase operation 3.0 to 5.5 20 30 ms tfw(2) ? programming operation 40 60 s power pin treatment recommendations (v dd 1, v ss 1) connect bypass capacitors that meet the following conditions between the v dd 1 and v ss 1 pins: ? connect among the v dd 1 and v ss 1pins and bypass capacitors c1 and c2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (l1=l1', l2=l2'). ? connect a large-capacity cap acitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should be approximately 0.1 f. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2
lc87f2608a no.a2175-20/23 figure 1 ac timing measurement point figure 2 oscillation stabilization times 0.5v dd operating v dd lower limit medium-speed rc oscillation power res medium-speed rc scillation high-speed rc oscillation operating mode reset time tmshrc unpredictable reset instruction execution reset time and oscillation stabilization time v dd 0v high-speed rc oscillation state hold/halt release signal no hold release signal hold release signal valid hold release signal and oscillation stabilization time hold halt instruction execution tmshrc halt release signal valid
lc87f2608a no.a2175-21/23 figure 3 sample reset circuit figure 4 serial i/o waveforms figure 5 pulse input timing signal waveform di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tpil tpih note: the external peripheral circuit differs depending on the way in which the power-on reset and low-voltage detection reset functions are used. refer to the chapter, entitled "reset function," of the user's manual. c res v dd r res res
lc87f2608a no.a2175-22/23 figure 6 example of por only (lvd deselected) mode waveforms (at reset pin with rres pull-up resistor only) ? the por circuit generates a reset signal only when the power voltage is raised from the v ss level. ? no stable reset signal is generated if power is turned on again when the power voltage does not go down to the v ss level as shown in (a). if this case is anticipated, use the lvd function as explained below or configure an external reset circuit. ? a reset is effected only when power is turned on ag ain after the power voltage goes down to and remains at the v ss level for 100 s or longer as shown in (b). figure 7 example of por + lvd mode waveforms (at reset pin with r res pull-up resistor only) ? a reset is effected both when power is turned on and when it goes down. ? the hysteresis width (lvhys) is introdu ced in the lvd circuit to prevent the iterations of the ic entering and exiting the reset state near th e detection threshold level. lvd voltage (lvdet) v dd res lvd hysteresis width (lvhys) reset unknown area (lvuks) reset period reset period reset period lvd release voltage (lvdet+lvhys) por release voltage (porrl) v dd res reset unknown area (pouks) (a) (b) reset period reset period 100 s or longer
lc87f2608a ps no.a2175-23/23 figure 8 minimum low voltage detection width (example of short interruption of power/ power fluctuation waveform) on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. v dd lvd voltage tlvdw v ss lvd release voltage lvdet-0.5v

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